Only two reasons..

Back in 2013 I presented to Mike Bartley’s “Future Verification”conference in Reading, UK. In this I boldly claimed that there were only two reasons for silicon failure:

1. The ASIC model failed or
2. The feature was not verified

It was slightly odd talking to an audience of dedicated verification engineers; like giving foxes strategy tips at a gamekeepers’ conference. But the two reasons are equally applicable to either designer or dedicated verification engineer, both must continually question if models are valid and question that the subset of features verified is sufficient.

The presentation was captured for posterity on Youtube, or look at the slides and notes. In Mike’s introduction I hoped he could have described the talk as “insightful” or maybe “big picture”, instead I got “off the wall”. I will allow you to judge…